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Micrel, Inc.
A bit synchronizer can be enabled in receive mode by
selecting the synchronous mode (Sync_en=1). The
DataClk pin will output a clock with twice the frequency of
the bit rate (a bit rate of 20 kbit/sec gives a DataClk of 20
kHz). A received symbol/bit on DataIXO will be output on
rising edge of DataClk. The micro controller should
therefore sample the symbol/bit on falling edge of DataClk.
MICRF600/MICRF600Z
Frequency Modulation
FSK modulation is applied by switching between two sets
of dividers (M,N,A). The formula for calculating the M, N
and A values is given in chapter Frequency synthesizer.
The divider values stored in the M0-, N0-, and A0-
registers will be used when transmitting a ‘0’ and the M1-,
N1-, and A1-registers will be used to transmit a ‘1’. The
The bit synchronizer uses a clock that needs to be
difference
between
the
two
carrier
frequencies
programmed according to the bit rate. The clock frequency
should be 16 times the actual bit rate (a bit rate of 20
kbit/sec needs a bit synchronizer clock with frequency of
320 kHz). The clock frequency is set by the following
formula:
corresponds to the double sided frequency deviation. The
data to be transmitted shall be applied to pin DataIXO (see
chapter Transceiver sync-/non-synchronous mode on how
to use the pin DataClk). The DataIXO pin is set as input in
transmit mode and output in receive mode.
f BITSYNC_CL K =
where
f XCO
Refclk_K × 2 (7 -BITSYNC_c lkS)
Using the XCO-tune Bits
The module has a built-in mechanism for tuning the
frequency of the crystal oscillator and is often used in
f BITSYNC_CLK : The bit synchronizer clock frequency
(16 times higher than the bit rate)
f XCO : Crystal oscillator frequency
Refclk_K: 6 bit divider, values between 1 and 63
BitSync_clkS: Bit synchronizer setting, values
between 0 and 7
Refclk_K is also used to derive the modulator clock and
the bit rate clock.
At the beginning of a received data package, the bit
synchronizer clock frequency is not synchronized to the bit
rate. When these two are maximum offset to each other, it
takes 22 bit/symbols before synchronization is achieved.
Transmitter
Power Amplifier
combination with the Frequency Error Estimator (FEE).
The XCO tuning is designed to eliminate or reduce initial
frequency tolerance of the crystal and/or the frequency
stability over temperature.
A procedure for using the XCO tuning feature in
combination with the FEE is given below. The MICRF600
measures the frequency offset between the receivers LO
frequency and the frequency of the transmitter. The
receiver XCO frequency can be tuned until the receiver
and transmitter frequencies are equal.
A procedure like this can be called during production
(storing the calibrated XCO_tune value), at regular
intervals or implemented in the communication protocol
when the frequency has changed. The MICRF600
development system can test this feature.
Example: In FEE, count up+down pulses, counting 8 bits:
A perfect case ==> FEE = 0
A6..A0
0000000
0000001
D7
LNA_by
‘1’
D6
PA2
‘0’
D5
PA1
‘0’
D4
PA0
‘0’
D3
Sync_en
RSSI_en
D2
Mode1
LD_en
D1
Mode0
PF_FC1
D0
’1’
PF_FC0
If FEE > 0: LO is too low, increase LO by decreasing
XCO_tune value
The maximum output power is approximately 10dBm for a
50 ? load. The output power is programmable in seven
steps, with approximately 3dB between each step. Bits
PA2 – PA0, control this. PA2 – PA0 = 1 give the maximum
output power.
The power amplifier can be turned off by setting PA2 –
PA0 = 0.
For all other combinations the PA is on and has maximum
power when PA2 – PA0 = 1.
The PA will be bypassed if PA_by=1. Output power will
drop ~14dB. It is still possible to control the power by PA2
– PA0.
v.v. for FEE < 0
FEE field holds a number in the range -128, … , 127.
However, it keeps counting above/below the range, which
is:
If FEE = -128 and still counting dwn-pulses:
1) =>-129 = +127
2) 126
3) 125
To avoid this situation, always make sure max count is
between limits.
July 2006
18
M9999-082505
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